1. Field of the Invention
The present invention relates to a semiconductor memory device operating in synchronism with an external clock signal.
2. Description of the Related Art
A conventional clock synchronous type semiconductor memory device is described in Japanese Laid Open Patent Application (JP-A-Heisei 8-129887). The structure and operation of the conventional clock synchronous type semiconductor memory device will be described with reference to FIG. 1. The conventional clock synchronous type semiconductor memory device operates in synchronism with an external clock signal and has a plurality of memory blocks called banks. Each of the banks is specified based on a bank address. Control signals and an address signal are supplied from external connection terminals in synchronism with the external clock signal. An internal clock signal ICLK is generated in synchronism with the external clock signal supplied from the external connection terminal and is supplied to each section of the memory device. A command is supplied through a plurality of control lines in synchronism with the clock signal. The inputted command is interpreted by a command decoder. The command decoder is a state machine, and determines the operation of the memory device based on the command. Then, the command decoder generates internal control signals such as row address strobe signals ARAS and BRAS, a column address strobe signal CAS, a read signal READ, a write signal WRITE, and a bank activation signal BANK in synchronism with the internal clock signal ICLK.
The bank 10 is composed of a memory cell array 13, latch circuits 17 and 18, a column address decoder 11, a row address decoder 12, a sense amplifier 14, a data amplifier 15 and a write amplifier 16.
The memory cell array 13 has a plurality of memory cells arranged in a matrix. The plurality of memory cells are connected one of word lines and one of bit lines. The latch circuit 17 receives the row address strobe signal ARAS and generates a word activation signal XE in synchronism with the internal clock signal ICLK. The latch circuit 18 generates a sense amplifier activation signal SE by delaying the word activation signal XE by one clock of the internal clock signal ICLK. The row address decoder 12 selects one of the word lines WL based on a row address signal XADD in synchronism with the word activation signal XE. The column address decoder 11 receives a column address signal YADD2 and a bank activation signal BANK, and selects one of bit line pairs BL in synchronism with the internal clock signal ICLK.
In case of a read operation, the sense amplifier 14 amplifies data read out from the memory cell array 13 on the selected bit line pair BL in response to the sense amplifier activation signal SE, and outputs a read data signal RO to the data amplifier 15. The data amplifier 15 amplifies the read data signal RO based on the bank activation signal BANK in response to a data amplifier activation signal DE and outputs the amplified data signal on an internal bus RWBUS. In case of a write operation, the write amplifier 16 amplifies a data signal on the internal bus RWBUS based on the bank activation signal BANK and output as a write data signal WI. The sense amplifier 14 amplifies the amplified write data signal WI on the selected bit line pair BL in response to the sense amplifier activation signal SE. Thus, the amplified signal is written in the memory cell array 13.
A read operation will be described in more detail with reference to FIGS. 2A to 2J.
First, an active command is issued to the bank 10 where a read data is stored. After that, a read command is issued to the activated bank to read out the data. Thus, the read operation is carried out through 2 steps, as shown in FIG. 2B.
When the active command is issued to the bank 10 at clock C4, the command decoder activates the row address strobe signal ARAS and the bank activation signal BANK is generated. The latch circuit 17 latches the row address strobe signal ARAS and delays the row address strobe signal ARAS by one clock of the internal clock signal ICLK to output as the word activation signal XE at clock C5, as shown in FIG. 2D. When the word activation signal XE is activated, one of the word lines WL is selected by the row address decoder 12, as shown in FIG. 2I. Also, the column address decoder 11 selects one of the bit line pairs BL based on the bank selection signal BANK and the column address signal YADD2. As a result, a voltage difference corresponding to the read data of the memory cell array 13 appears on the selected bit line pair BL, as shown in FIG. 2H.
The latch circuit 18 delays the word activation signal XE by one clock of the internal clock signal ICLK such that the sense amplifier activation signal SE is activated at clock C6, as shown in FIG. 2E. The voltage difference on the selected bit line pair BL is amplified by the sense amplifier 14 when the sense amplifier activation signal SE is activated. Thus, the operation of the active command to the bank 10 is completed.
After that, the read command is inputted and the operation moves to the read operation. The read command to the same bank is issued after a time determined based on the operating time of the circuit after the active command is issued. FIGS. 2A to 2J are an example that the read command is issued to another bank 20. Therefore, a read command is issued at clock C5. Because the operation after the read command is issued is the same, it is supposed that the read command is issued one to the bank 10 at clock C5.
When the read command to the bank 10 is issued in the clock C5, the read signal READ is activated and the read operation to the bank 10 is started. The data amplifier activation signal DE is activated in synchronism with the internal clock signal ICLK at clock C6 and the data amplifier 15 is activated. When the data amplifier 15 is activated, the read data is transferred onto the internal bus RWBUS. The read data transferred onto the internal bus RWBUS is latched by the latch circuit and is then outputted to an external unit.
In this way, a time until the sense amplifier activation signal SE is activated after the word activation signal XE is activated corresponds to one cycle of the external clock signal independently from the influence of a process condition, a temperature condition and a voltage condition.
In DRAM in recent years, the external clock signal of 300/400 MHz (one time period of 3.3/2.5 ns) is used. FIG. 3 shows a circuit which generates the word activation signal XE and the sense amplifier activation signal SE. This circuit is equivalent to a circuit of the latch circuit 17 and the latch circuit 18 shown in FIG. 5 and is composed of a delay circuit 72, a shift register 71 of a 5-stage of flip-flops operating in synchronism with the internal clock signal ICLK. The delay circuit 72 delays the row address strobe signal ARAS by γ time and generates the word activation signal XE. The shift register 71 delays the row address strobe signal ARAS and generates the sense amplifier activation signal SE. The delay circuit 72 functions as a buffer to transfer the word activation signal XE, and the delay time γ is very small. A time until the sense amplifier activation signal SE is activated after the word activation signal XE is activated is determined based on a time when data is read out from the memory cell array 13 onto the selected bit line pair BL. If the sense amplifier activation signal SE is activated to drive the sense amplifier 14 when the voltage difference on the selected bit line pair BL is not large, an erroneous operation is caused. Therefore, the time until the sense amplifier activation signal SE is activated after the word activation signal XE is activated can not be simply shortened even if the frequency of the external clock signal is made high. In the above example, the time is 12.5 ns. In case of the external clock signal of 400 MHz, the sense amplifier activation signal SE is generated by a shift register 71 after the row address strobe signal ARAS by five clocks (12.5 ns) of the internal clock signal ICLK.
FIGS. 4A to 4F are timing charts showing an operation when the external clock signal has the frequency of 400 MHz. The shortest time until the read command is issued after the active command is issued is tRCDmin which is set to be 7 clocks of the external clock signal (17.5 ns), considering the operating time of the circuit. When the active command is received at clock C0, the row address strobe signal ARAS is activated and the word activation signal XE is activated by a delay circuit 72 of FIG. 3. The row address strobe signal ARAS is delayed by the shift register 71 and the sense amplifier activation signal SE is activated at clock c5 after 5 clocks from the row address strobe signal ARAS. When the read command is received at clock C7, the data amplifier activation signal DE is activated.
By the way, although being not written in Japanese Laid Open Patent Application (JP-A-Heisei 08-129887), it is well known that the sense amplifier selection signal YS is activated before the data amplifier activation signal DE is activated, and the read data with a small voltage difference appears as the read data signal RO. When the read command is received, the sense amplifier selection signal YS is first activated. Then, after read data with the small voltage difference is outputted as the read data signal RO, the data amplifier activation signal DE is activated to amplify the read data signal RO.
As described above, the time until the sense amplifier activation signal SE is activated after the row address strobe signal ARAS is activated is 12.5 ns, and the time until the sense amplifier selection signal YS is activated after the sense amplifier activation signal SE is activated is 5.0 ns. These delay times depend on the period of the external clock signal and are kept 12.5 ns and 5.0 ns without depending on influences of a process condition, a temperature condition, and a voltage change.
FIGS. 5A to 5F are timing charts showing the operation when the external clock signal has the frequency of 300 MHz. If the read command is issued after seven clocks from the issuing time of the active command, like the 400-MHz operation, the shortest time tRCDmin until the read command is issued after the active command is issued is 23.1 ns. In this case, because the efficiency drops from 17.5 ns in case of the 400-MHz operation to 23.1 ns in the 300-MHz operation, the delay time is generally set to six clocks in case of the 300-MHz operation to shorten the shortest time tRCDmin to 19.8 ns.
In this case, the time until the sense amplifier activation signal SE is activated after the row address strobe signal ARAS is activated is 16.5 ns for five clocks of the internal clock signal CLK. The time tRCDmin is 19.8 ns because it is equivalent to six clocks of the internal clock signal ICLK. The time until the sense amplifier selection signal YS is activated after the sense amplifier activation signal SE is activated is 3.3 ns. In this case, a necessary delay can not be achieved and the degradation of the sense margin is led and the stable operation is impossible.
To overcome this problem, it is necessary that the time tRCDmin is set to seven clocks (23.1 ns) or a delay represented by an inverter chain which generate a delay time without depending on the clock signal period is used for a circuit which generates the sense amplifier activation signal SE, under permission of the efficiency degradation. However, it is difficult that the delay of the inverter chain achieves the operation margin stable in all the conditions because it changes depending on a process condition, a temperature condition, and a voltage change.
The technique for excluding the dependency of a clock signal on the power supply voltage and temperature and so on, the following technique is known in Japanese Laid Open Patent Application (JP-P2000-285687A). In this technique, in a synchronous type mask ROM, the pulse widths of a sense amplifier activation signal and a latch signal are determined in synchronism with the rising edge or falling edge of the clock signal after the number of cycles determined in accordance with the number of clocks of a preset latency from a command input signal.
Also, a sense amplifier enable signal generating apparatus is described in Japanese Laid Open Patent Application (JP-A-Heisei 10-199251). In this conventional example, a count section inputs a RASB signal to select a row address of a memory cell array, and a signal is outputted in synchronism with a clock signal. The operation of the count section is stopped when the input of the RASB signal is stopped. A comparator outputs the sense amplifier enable signal to indicate the operation start of a sense amplifier when the count value outputted by the count section reaches a programmed delay time and stops the output of the sense amplifier enable signal when the input of the RASB signal is stopped.